Radio-frequency switches with distorter arms and voltage buffers

ABSTRACT

Disclosed herein are systems and methods for reducing intermodulation distortion (IMD) in switches using distorter circuits and voltage buffers. A switch circuit can include a switch arm with a stack of field-effect transistors (FETs), a distorter arm that is configured to act as a compensation circuit to compensate for non-linearities in the switch arm, and a voltage buffer that is configured to protect the distorter arm from large voltage swings when transitioning between ON and OFF states. The gate width of the distorter arm can be orders of magnitude smaller than the gate widths of the switch FETs. The gate width of the voltage buffer FETs can be larger than the distorter arm and smaller than the switch arm. The distorter arm is configured to compensate for the non-linearity effect generated by the switch arm.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.15/851,810 filed Dec. 22, 2017 and entitled “SWITCH LINEARIZATION BYCOMPENSATION OF A FIELD-EFFECT TRANSISTOR,” which claims priority toU.S. Provisional Application No. 62/438,773 filed Dec. 23, 2016 andentitled “SWITCH LINEARIZATION BY COMPENSATION OF A FIELD-EFFECTTRANSISTOR,” which is expressly incorporated by reference herein in itsentirety for all purposes.

This application is also related to U.S. Pat. Pub. No. 2014/0009214,filed Jul. 6, 2013 and published Jan. 9, 2014, entitled “Circuits,devices, methods and applications related to silicon-on-insulator basedradio-frequency switches,” which is expressly incorporated by referenceherein in its entirety for all purposes.

BACKGROUND Field

The present disclosure generally relates to the field of electronics,and more particularly, to radio-frequency switches.

Description of Related Art

Radio-frequency (RF) switches, such as transistor switches, can be usedto switch signals between one or more poles and one or more throws.Transistor switches, or portions thereof, can be controlled throughtransistor biasing and/or coupling. Design and use of bias and/orcoupling circuits in connection with RF switches can affect switchingperformance.

SUMMARY

According to a number of implementations, the present disclosure relatesto a radio-frequency switch that includes a switch arm having a set offield-effect transistors disposed between a first node and a secondnode, each field-effect transistor of the set of field-effecttransistors having a respective source, drain, gate, and body; and adistorter arm coupled in parallel to the switch arm, the distorter armhaving a non-linear resistor or a field-effect transistor, the distorterarm configured to compensate a non-linearity effect generated by the setof field-effect transistors in the switch arm.

In some embodiments, the one or more field-effect transistors of thedistorter arm have a gate width that is smaller than about 10 μm and theset of field-effect transistors of the switch arm have a gate width thatis larger than about 1 mm. In some embodiments, the set of field-effecttransistors of the switch arm includes at least 12 field-effecttransistors.

In some embodiments, the radio-frequency switch further includes avoltage buffer coupled in series with the distorter arm and in parallelwith the switch arm, the voltage buffer including a set of field-effecttransistors. In further embodiments, the set of field-effect transistorsof the voltage buffer each have a gate width that is larger than a gatewidth of the field-effect transistor of the distorter arm and smallerthan a gate width of each field-effect transistor in the switch arm. Infurther embodiments, in an ON state of the radio-frequency switch, thevoltage buffer, the switch arm, and the distorter arm are configured tobe in an ON state. In yet further embodiments, in an OFF state of theradio-frequency switch, the voltage buffer and the switch arm areconfigured to be in an OFF state and the distorter arm is configured tobe in an ON state.

In some embodiments, the radio-frequency switch further includes asecond distorter arm coupled in parallel to the switch arm and to thedistorter arm, the second distorter arm having a non-linear resistor ora field-effect transistor. In further embodiments, the radio-frequencyswitch further includes a voltage supply configured to provide a firstdrain-source voltage on the field-effect transistor of the distorter armand to provide a second drain-source voltage on the field-effecttransistor of the second distorter arm, wherein the first drain-sourcevoltage and the second drain-source voltage have the same magnitude andopposite polarity. In further embodiments, the radio-frequency switchfurther includes a first DC-blocking capacitor having a first endcoupled to a junction between the first node and the switch arm and asecond end coupled to the distorter arm and a second DC-blockingcapacitor having a first end coupled to a junction between the secondnode and the switch arm and a second end coupled to the distorter arm.In further embodiments, the distorter arm and the second distorter armare each configured to compensate the non-linearity effect by generatingthird-order intermodulation distortion and the distorter arm and thesecond distorter arm do not increase second-order harmonic distortion ofthe radio-frequency switch. In further embodiments, the radio frequencyswitch further includes a biasing circuit having at least two currentsources to drive currents to the distorter arm and to the seconddistorter arm. In yet further embodiments, the at least two currentsources generate a current loop in the biasing circuit, the current loopbeing formed with the distorter arm, the second distorter arm, and theat least two current sources. In yet further embodiments, due at leastin part to high impedance of the at least two current sources, thebiasing circuit reduces RF choke between a DC bias source and thedistorter arm and the second distorter arm.

In some embodiments, the distorter arm is configured to generatethird-order intermodulation distortion to reduce the non-linearityeffect generated by the set of field-effect transistors in the switcharm. In some embodiments, the set of field-effect transistors comprisesilicon-on-insulator (SOI) set of field-effect transistors.

According to a number of implementations, the present disclosure relatesto a radio-frequency switch module that includes a packaging substrateconfigured to receive a plurality of components and a semiconductor diemounted on the packaging substrate, the semiconductor die including aset of field-effect transistors in a switch arm. The module alsoincludes a distorter arm mounted on the packaging substrate coupled inparallel with the set of field-effect transistors of the switch arm, thedistorter arm having one or more field-effect transistors that areconfigured to compensate a non-linearity effect generated by the set offield-effect transistors of the switch arm.

In some embodiments, the radio-frequency switch module further includesa voltage buffer mounted on the packaging substrate, the voltage buffercoupled in series with the distorter arm and combination of thedistorter arm and the voltage buffer coupled in parallel with the switcharm.

According to a number of implementations, the present disclosure relatesto a wireless device that includes a transceiver configured to processradio-frequency (RF) signals, an antenna in communication with thetransceiver configured to facilitate transmission of an amplified RFsignal, and a power amplifier connected to the transceiver andconfigured to generate the amplified RF signal. The wireless device alsoincludes a switch connected to the antenna and the power amplifier andconfigured to selectively route the amplified RF signal to the antenna,the switch including a set of field-effect transistors in a switch arm,and a distorter arm coupled in parallel with the set of field-effecttransistors of the switch arm, the distorter arm having one or morefield-effect transistors that are configured to compensate anon-linearity effect generated by the set of field-effect transistors ofthe switch arm.

In some embodiments, the switch further includes a second distortercoupled in parallel with the set of field-effect transistors of theswitch arm, the second distorter arm having one or more field-effecttransistors, the combination of the distorter arm and the seconddistorter arm configured to compensate a non-linearity effect generatedby the set of field-effect transistors of the switch arm.

For purposes of summarizing the disclosure, certain aspects, advantagesand novel features have been described herein. It is to be understoodthat not necessarily all such advantages may be achieved in accordancewith any particular embodiment. Thus, the disclosed embodiments may becarried out in a manner that achieves or optimizes one advantage orgroup of advantages as taught herein without necessarily achieving otheradvantages as may be taught or suggested herein.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a schematic representation of a radio-frequency (RF)switch configured to switch one or more signals between one or morepoles and one or more throws.

FIG. 2 illustrates that, in some implementations, the RF switch of FIG.1 can include an RF core and an energy management (EM) core.

FIG. 3 illustrates an example configuration of an RF core for the RFswitch of FIG. 1.

FIG. 4 illustrates an example RF core configuration having switch armsegments and shunt arm segments.

FIG. 5 illustrates that, in some implementations, control of afield-effect transistor (FET) can be facilitated by a circuit configuredto bias and/or couple one or more portions of the FET.

FIG. 6 illustrates an example configuration of a portion of a switch toillustrate biasing and/or coupling of different parts of one or moreFETs.

FIGS. 7A and 7B illustrate plan and side sectional views of an examplefinger-based FET device implemented on silicon-on-insulator (SOI).

FIGS. 8A and 8B illustrate plan and side sectional views of an examplemultiple-finger FET device implemented on SOI.

FIG. 9 illustrates an example switch circuit having a switch arm and adistorter arm that is configured to act as a compensation circuit tocompensate for non-linearities in the switch arm.

FIG. 10 illustrates curves for the third derivative of the draincurrent, gd3, as a function of drain-source voltage, Vds or Vd, anddemonstrates that gd3 relates to a physical size of the FET.

FIGS. 11A, 11B, and 11C illustrate plots showing compensation of gd3 ofa switch arm having a stack of FETs by a distorter arm having one ormore FETs.

FIG. 12 illustrates results of a simulation of the switch circuitdescribed herein with reference to FIG. 11, operating to switch signalswith two fundamental frequencies.

FIG. 13 illustrates an example switch circuit that includes dualparallel distorter arms in parallel with a switch arm that is configuredto reduce or at least not significantly increase harmonic distortionwhile decreasing IMD3 non-linearity in the switch circuit.

FIG. 14 illustrates results of a simulation of the switch circuitdescribed herein with reference to FIG. 13, operating to switch signalswith two fundamental frequencies.

FIG. 15 illustrates an example switch circuit that includes dualparallel distorter arms in parallel with a switch arm that is configuredto reduce or at least not significantly increase harmonic distortionwhile decreasing IMD3 non-linearity in the switch circuit.

FIG. 16 illustrates results of a simulation of the switch circuitdescribed herein with reference to FIG. 15, operating to switch signalswith two fundamental frequencies.

FIG. 17 illustrates a portion of a switch circuit having a switch armwith multiple FETs and a distorter arm that includes fewer, smallerFETs.

FIG. 18 illustrates an example switch circuit with a switch arm,distorter arm, and a voltage buffer in series with the distorter arm.

FIG. 19 illustrates a plot of the DC power consumption of the switchcircuit of FIG. 18 as a function of gate width of the voltage buffer.

FIG. 20 illustrates various plots of performance of the switch circuitof FIG. 18 configured as a DPDT switch.

FIG. 21 illustrates another example switch circuit configured similarlyto the switch circuit of FIG. 18 but having a non-linear resistor in thedistorter arm rather than a FET.

FIG. 22 illustrates an example biasing circuit for a switch circuit, asdescribed herein.

FIGS. 23A, 23B, 23C, and 23D schematically illustrate non-limitingexamples of implementations of the switch circuits described herein onone or more semiconductor die.

FIGS. 24A and 24B illustrate that one or more die having one or morefeatures described herein can be implemented in a packaged module.

FIG. 25 illustrates a schematic diagram of an example switchingconfiguration that can be implemented in the module of FIGS. 24A and24B.

FIG. 26 illustrates that in some embodiments, some or all of the deviceshaving one or more features as described herein may be implemented in amodule.

FIG. 27 illustrates an example wireless device having one or moreadvantageous features described herein.

DETAILED DESCRIPTION OF SOME EMBODIMENTS

The headings provided herein, if any, are for convenience only and donot necessarily affect the scope or meaning of the claimed invention.

Example Components of a Switching Device

FIG. 1 schematically shows a radio-frequency (RF) switch 100 configuredto switch one or more signals between one or more poles 102 and one ormore throws 104. In some embodiments, such a switch can be based on oneor more field-effect transistors (FETs) such as silicon-on-insulator(SOI) FETs. When a particular pole is connected to a particular throw,such a path is commonly referred to as being closed or in an ON state.When a given path between a pole and a throw is not connected, such apath is commonly referred to as being open or in an OFF state. Theswitch 100 can include coupling circuits, such as parallel distortercircuits disclosed herein, that are configured to improve performance ofthe switch. For example, parallel distorter circuits disclosed hereincan generate signals that reduce or eliminate non-linearities in theswitch 100.

FIG. 2 shows that in some implementations, the RF switch 100 of FIG. 1can include an RF core 110 and an energy management (EM) core 112. TheRF core 110 can be configured to route RF signals between the first andsecond ports. In the example single-pole-double-throw (SPDT)configuration shown in FIG. 2, such first and second ports can include apole 102 a and a first throw 104 a, or the pole 102 a and a second throw104 b.

In some embodiments, EM core 112 can be configured to supply, forexample, voltage control signals to the RF core. The EM core 112 can befurther configured to provide the RF switch 100 with logic decodingand/or power supply conditioning capabilities.

In some embodiments, the RF core 110 can include one or more poles andone or more throws to enable passage of RF signals between one or moreinputs and one or more outputs of the switch 100. For example, the RFcore 110 can include a single-pole double-throw (SPDT or SP2T)configuration as shown in FIG. 2.

In the example SPDT context, FIG. 3 shows a more detailed exampleconfiguration of an RF core 110. The RF core 110 is shown to include asingle pole 102 a coupled to first and second throw nodes 104 a, 104 bvia first and second transistors (e.g., FETs) 120 a, 120 b. The firstthrow node 104 a is shown to be coupled to an RF ground via FET 122 a toprovide shunting capability for the node 104 a. Similarly, the secondthrow node 104 b is shown to be coupled to the RF ground via FET 122 bto provide shunting capability for the node 104 b.

In an example operation, when the RF core 110 is in a state where an RFsignal is being passed between the pole 102 a and the first throw 104 a,the FET 120 a between the pole 102 a and the first throw node 104 a canbe in an ON state, and the FET 120 b between the pole 102 a and thesecond throw node 104 b can be in an OFF state. For the shunt FETs 122a, 122 b, the shunt FET 122 a can be in an OFF state so that the RFsignal is not shunted to ground as it travels from the pole 102 a to thefirst throw node 104 a. The shunt FET 122 b associated with the secondthrow node 104 b can be in an ON state so that any RF signals or noisearriving at the RF core 110 through the second throw node 104 b isshunted to the ground to reduce undesirable interference effects to thepole-to-first-throw operation.

Although the foregoing example is described in the context of asingle-pole-double-throw configuration, it will be understood that theRF core can be configured with other numbers of poles and throws. Forexample, there may be more than one pole, and the number of throws canbe less than or greater than the example number of two.

In the example of FIG. 3, the transistors between the pole 102 a and thetwo throw nodes 104 a, 104 b are depicted as single transistors. In someimplementations, such switching functionalities between the pole(s) andthe throw(s) can be provided by switch arm segments, where each switcharm segment includes a plurality of transistors such as FETs.

An example RF core configuration 130 of an RF core having such switcharm segments is shown in FIG. 4. In the example, the pole 102 a and thefirst throw node 104 a are shown to be coupled via a first switch armsegment 140 a. Similarly, the pole 102 a and the second throw node 104 bare shown to be coupled via a second switch arm segment 140 b. The firstthrow node 104 a is shown to be capable of being shunted to an RF groundvia a first shunt arm segment 142 a. Similarly, the second throw node104 b is shown to be capable of being shunted to the RF ground via asecond shunt arm segment 142 b.

In an example operation, when the RF core 130 is in a state where an RFsignal is being passed between the pole 102 a and the first throw node104 a, all of the FETs in the first switch arm segment 140 a can be inan ON state, and all of the FETs in the second switch arm segment 104 bcan be in an OFF state. The first shunt arm 142 a for the first thrownode 104 a can have all of its FETs in an OFF state so that the RFsignal is not shunted to ground as it travels from the pole 102 a to thefirst throw node 104 a. All of the FETs in the second shunt arm 142 bassociated with the second throw node 104 b can be in an ON state sothat any RF signals or noise arriving at the RF core 130 through thesecond throw node 104 b is shunted to the ground to reduce undesirableinterference effects to the pole-to-first-throw operation.

Again, although described in the context of an SP2T configuration, itwill be understood that RF cores having other numbers of poles andthrows can also be implemented.

In some implementations, a switch arm segment (e.g., 140 a, 140 b, 142a, 142 b) can include one or more semiconductor transistors such asFETs. In some embodiments, a FET may be capable of being in a firststate or a second state and can include a gate, a drain, a source, and abody (sometimes also referred to as a substrate). In some embodiments, aFET can include a metal-oxide-semiconductor field effect transistor(MOSFET). In some embodiments, one or more FETs can be connected inseries forming a first end and a second end such that an RF signal canbe routed between the first end and the second end when the FETs are ina first state (e.g., ON state). A series of coupled FETs can be referredto as a stack, a stack of FETs, or a FET stack.

At least some of the present disclosure relates to how a FET or a groupof FETs can be controlled to provide switching functionalities indesirable manners. FIG. 5 schematically shows that in someimplementations, such controlling of a FET 120 can be facilitated by acircuit 150 configured to bias and/or couple one or more portions of theFET 120. In some embodiments, such a circuit 150 can include one or morecircuits configured to bias and/or couple a gate of the FET 120, biasand/or couple a body of the FET 120, and/or couple a source/drain of theFET 120.

Schematic examples of how such biasing and/or coupling of differentparts of one or more FETs are described in reference to FIG. 6. In FIG.6, a switch arm segment 140 (that can be, for example, one of theexample switch arm segments 140 a, 140 b, 142 a, 142 b of the example ofFIG. 4) between nodes 144, 146 is shown to include a plurality of FETs120. Operations of such FETs can be controlled and/or facilitated bygate bias/coupling circuit(s) 150 a, body bias/coupling circuit(s) 150c, and/or source/drain coupling circuit(s) 150 b.

Gate Bias/Coupling Circuit

In the example shown in FIG. 6, the gate of each of the FETs 120 can beconnected to the gate bias/coupling circuit 150 a to receive a gate biassignal and/or to couple the gate to another part of the FET 120 or theswitch arm 140. In some implementations, designs or features of the gatebias/coupling circuit 150 a can improve performance of the switch arm140. Such improvements in performance can include, but are not limitedto, device insertion loss, isolation performance, power handlingcapability, and/or switching device linearity. Example gatebias/coupling circuits are discussed in more detail in U.S. Pat. Pub.No. 2014/0009214, filed Jul. 6, 2013 and published Jan. 9, 2014,entitled “Circuits, devices, methods and applications related tosilicon-on-insulator based radio-frequency switches,” which is expresslyincorporated by reference herein in its entirety.

Body Bias/Coupling Circuit

As shown in FIG. 6, the body of each FET 120 can be connected to thebody bias/coupling circuit 150 c to receive a body bias signal and/or tocouple the body to another part of the FET 120 or the switch arm 140. Insome implementations, designs or features of the body bias/couplingcircuit 150 c can improve performance of the switch arm 140. Suchimprovements in performance can include, but are not limited to, deviceinsertion loss, isolation performance, power handling capability, and/orswitching device linearity. Example body bias/coupling circuits arediscussed in more detail in U.S. Pat. Pub. No. 2014/0009214, filed Jul.6, 2013 and published Jan. 9, 2014, entitled “Circuits, devices, methodsand applications related to silicon-on-insulator based radio-frequencyswitches,” which is expressly incorporated by reference herein in itsentirety.

Source/Drain Coupling Circuit

As shown in FIG. 6, the source/drain of each FET 120 can be connected tothe source/drain coupling circuit 150 b to couple the source/drain toanother part of the FET 120 or the switch arm 140. In someimplementations, designs or features of the source/drain couplingcircuit 150 b can improve performance of the switch arm 140. Suchimprovements in performance can include, but are not limited to, deviceinsertion loss, isolation performance, power handling capability, and/orswitching device linearity. Example coupling circuits are discussed inmore detail in U.S. Pat. Pub. No. 2014/0009214, filed Jul. 6, 2013 andpublished Jan. 9, 2014, entitled “Circuits, devices, methods andapplications related to silicon-on-insulator based radio-frequencyswitches,” which is expressly incorporated by reference herein in itsentirety.

Examples of Switching Performance Parameters

Insertion Loss

A switching device performance parameter can include a measure ofinsertion loss. A switching device insertion loss can be a measure ofthe attenuation of an RF signal that is routed through the RF switchingdevice. For example, the magnitude of an RF signal at an output port ofa switching device can be less than the magnitude of the RF signal at aninput port of the switching device. In some embodiments, a switchingdevice can include device components that introduce parasiticcapacitance, inductance, resistance, or conductance into the device,contributing to increased switching device insertion loss. In someembodiments, a switching device insertion loss can be measured as aratio of the power or voltage of an RF signal at an input port to thepower or voltage of the RF signal at an output port of the switchingdevice. Decreased switching device insertion loss can be desirable toenable improved RF signal transmission.

Isolation

A switching device performance parameter can also include a measure ofisolation. Switching device isolation can be a measure of the RFisolation between an input port and an output port an RF switchingdevice. In some embodiments, it can be a measure of the RF isolation ofa switching device while the switching device is in a state where aninput port and an output port are electrically isolated, for examplewhile the switching device is in an OFF state. Increased switchingdevice isolation can improve RF signal integrity. In certainembodiments, an increase in isolation can improve wireless communicationdevice performance.

Intermodulation Distortion

A switching device performance parameter can further include a measureof intermodulation distortion (IMD) performance. Intermodulationdistortion (IMD) can be a measure of non-linearity in an RF switchingdevice.

IMD can result from two or more signals mixing together and yieldingfrequencies that are not harmonic frequencies. For example, suppose thattwo signals have fundamental frequencies f1 and f2 (f2>f1) that arerelatively close to each other in frequency space. Mixing of suchsignals can result in peaks in frequency spectrum at frequenciescorresponding to different products of fundamental and harmonicfrequencies of the two signals. For example, a second-orderintermodulation distortion (also referred to as IMD2) is typicallyconsidered to include frequencies f1+f2, f2−f1, 2f1, and 2f2. Athird-order IMD (also referred to as IMD3) is typically considered toinclude 2f1+f2, 2f1−f2, f1+2f2, f1−2f2. Higher order products can beformed in similar manners.

In general, as the IMD order number increases, power levels decrease.Accordingly, second and third orders can be undesirable effects that areof particular interest. Higher orders such as fourth and fifth orderscan also be of interest in some situations.

In some RF applications, it can be desirable to reduce susceptibility tointerference within an RF system. Non-linearity in RF systems can resultin introduction of spurious signals into the system. Spurious signals inthe RF system can result in interference within the system and degradethe information transmitted by RF signals. An RF system having increasednon-linearity can demonstrate increased susceptibility to interference.Non-linearity in system components, for example switching devices, cancontribute to the introduction of spurious signals into the RF system,thereby contributing to degradation of overall RF system linearity andIMD performance.

In some embodiments, RF switching devices can be implemented as part ofan RF system including a wireless communication system. IMD performanceof the system can be improved by increasing linearity of systemcomponents, such as linearity of an RF switching device. In someembodiments, a wireless communication system can operate in a multi-bandand/or multi-mode environment. Improvement in intermodulation distortion(IMD) performance can be desirable in wireless communication systemsoperating in a multi-band and/or multi-mode environment. In someembodiments, improvement of a switching device IMD performance canimprove the IMD performance of a wireless communication system operatingin a multi-mode and/or multi-band environment.

Improved switching device IMD performance can be desirable for wirelesscommunication devices operating in various wireless communicationstandards, for example for wireless communication devices operating inthe LTE communication standard. In some RF applications, it can bedesirable to improve linearity of switching devices operating inwireless communication devices that enable simultaneous transmission ofdata and voice communication. For example, improved IMD performance inswitching devices can be desirable for wireless communication devicesoperating in the LTE communication standard and performing simultaneoustransmission of voice and data communication (e.g., SVLTE).

High Power Handling Capability

In some RF applications, it can be desirable for RF switching devices tooperate under high power while reducing degradation of other deviceperformance parameters. In some embodiments, it can be desirable for RFswitching devices to operate under high power with improvedintermodulation distortion, insertion loss, and/or isolationperformance.

In some embodiments, an increased number of transistors can beimplemented in a switch arm segment of a switching device to enableimproved power handling capability of the switching device. For example,a switch arm segment can include an increased number of FETs connectedin series, an increased FET stack height, to enable improved deviceperformance under high power. However, in some embodiments, increasedFET stack height can degrade the switching device insertion lossperformance.

Examples of FET Structures and Fabrication Process Technologies

A switching device can be implemented on-die, off-die, or somecombination thereon. A switching device can also be fabricated usingvarious technologies. In some embodiments, RF switching devices can befabricated with silicon or silicon-on-insulator (SOI) technology.

As described herein, an RF switching device can be implemented usingsilicon-on-insulator (SOI) technology. In some embodiments, SOItechnology can include a semiconductor substrate having an embeddedlayer of electrically insulating material, such as a buried oxide layerbeneath a silicon device layer. For example, an SOI substrate caninclude an oxide layer embedded below a silicon layer. Other insulatingmaterials known in the art can also be used.

Implementation of RF applications, such as an RF switching device, usingSOI technology can improve switching device performance. In someembodiments, SOI technology can enable reduced power consumption.Reduced power consumption can be desirable in RF applications, includingthose associated with wireless communication devices. SOI technology canenable reduced power consumption of device circuitry due to decreasedparasitic capacitance of transistors and interconnect metallization to asilicon substrate. Presence of a buried oxide layer can also reducejunction capacitance or use of high resistivity substrate, enablingreduced substrate related RF losses. Electrically isolated SOItransistors can facilitate stacking, contributing to decreased chipsize.

In some SOI FET configurations, each transistor can be configured as afinger-based device where the source and drain are rectangular shaped(in a plan view) and a gate structure extends between the source anddrain like a rectangular shaped finger. FIGS. 7A and 7B show plan andside sectional views of an example finger-based FET device implementedon SOI. As shown, FET devices described herein can include a p-type FETor an n-type FET. Thus, although some FET devices are described hereinas p-type devices, it will be understood that various conceptsassociated with such p-type devices can also apply to n-type devices.

As shown in FIGS. 7A and 7B, a pMOSFET can include an insulator layerformed on a semiconductor substrate. The insulator layer can be formedfrom materials such as silicon dioxide or sapphire. An n-well is shownto be formed in the insulator such that the exposed surface generallydefines a rectangular region. Source (S) and drain (D) are shown to bep-doped regions whose exposed surfaces generally define rectangles. Asshown, S/D regions can be configured so that source and drainfunctionalities are reversed.

FIGS. 7A and 7B further show that a gate (G) can be formed on the n-wellso as to be positioned between the source and the drain. The examplegate is depicted as having a rectangular shape that extends along withthe source and the drain. Also shown is an n-type body contact.Formations of the rectangular shaped well, source and drain regions, andthe body contact can be achieved by a number of known techniques. Insome embodiments, the source and drain regions can be formed adjacent tothe ends of their respective upper insulator layers, and the junctionsbetween the body and the source/drain regions on the opposing sides ofthe body can extend substantially all the way down to the top of theburied insulator layer. Such a configuration can provide, for example,reduced source/drain junction capacitance. To form a body contact forsuch a configuration, an additional gate region can be provided on theside so as to allow, for example, an isolated P+ region to contact thePwell.

FIGS. 8A and 8B show plan and side sectional views of an example of amultiple-finger FET device implemented on SOI. Formations of rectangularshaped n-well, rectangular shaped p-doped regions, rectangular shapedgates, and n-type body contact can be achieved in manners similar tothose described in reference to FIGS. 7A and 7B.

The example multiple-finger FET device of FIGS. 8A and 8B can be made tooperate such that a drain of one FET acts as a source of its neighboringFET. Thus, the multiple-finger FET device as a whole can provide avoltage-dividing functionality. For example, an RF signal can beprovided at one of the outermost p-doped regions (e.g., the leftmostp-doped region); and as the signal passes through the series of FETs,the signal's voltage can be divided among the FETs. In such an example,the rightmost p-doped region can act as an overall drain of themulti-finger FET device.

In some implementations, a plurality of the foregoing multi-finger FETdevices can be connected in series as a switch to, for example, furtherfacilitate the voltage-dividing functionality. A number of suchmulti-finger FET devices can be selected based on, for example, powerhandling requirement of the switch.

Examples of Bias and/or Coupling Configurations for Improved Performance

Described herein are various examples of how FET-based switch circuitscan be biased and/or coupled to yield one or more performanceimprovements. In some embodiments, such biasing/coupling configurationscan be implemented in SOI FET-based switch circuits. It will beunderstood that some of the example biasing/coupling configurations canbe combined to yield a combination of desirable features that may not beavailable to the individual configurations. It will also be understoodthat, although described in the context of RF switching applications,one or more features described herein can also be applied to othercircuits and devices that utilize FETs such as SOI FETs.

Example Configurations of Switch Circuits

In some radio-frequency (RF) applications, it is desirable to utilizeswitches having high linearity, as well as management of intermodulationdistortion (IMD) such as IMD3 and IMD2. Such switch-related performancefeatures can contribute significantly to system-level performance ofcellular devices. In the context of silicon-on-oxide (SOI) switches,factors such as substrate-coupling (sometimes also referred to assubstrate parasitics) and SOI-process can limit the performanceachievable.

Such a limitation in performance of SOI switches can be addressed byextensive substrate crosstalk reduction techniques such as capacitiveguard rings, and/or trap rich or deep trench isolation techniques. Suchtechniques typically have associated with them undesirable features suchas being expensive, requiring relatively large areas, and requiringadditional process steps. Also, such techniques can yield a desirableeffect that is limited to an isolation feature.

In some implementations, performance of SOI switches can be improved byovercoming or reducing the foregoing effects associated with substrateparasitics and/or process variables. Accordingly, disclosed herein aresystems and methods for reducing IMD in switches using paralleldistorter circuits. By way of an example, FIG. 9 illustrates an exampleswitch circuit 1100 having a switch arm 1105 and a distorter arm 1103,configured to act as a compensation circuit to compensate fornon-linearities in the switch arm 1105. The switch circuit 1100 caninclude a plurality of FETs in the switch arm 1105 (e.g., a set, stack,or group of FETs) configured to provide switching functionality betweena first node 1101 and a second node 1102. In certain embodiments, one ormore of the FETs may be an SOI FET. In the switch arm 1105, individualFETs may include a gate, a body, a source, and a drain. A gate (e.g., agate terminal) of a FET may be biased by a bias voltage provided by agate bias circuit (not illustrated in FIG. 9) which may be coupled tothe gate. A body (e.g., a body terminal) of a FET may be biased by abias voltage provided by a body bias circuit (not illustrated in FIG. 9)which may be coupled to the body. In various embodiments, the first node1101 may be an input node and may receive a signal, such as an RFsignal. The second node 1102 may be an output node and may output thesignal (such as an RF signal). The switch arm 1105 may output the signal(received at the first node 1101) via the second node 1102 when theswitch arm 1105 is in an ON state (e.g., when the one or more FETs is inan ON state). The switch arm 1105, via the one or more FETs, may prevent(may stop) a signal received at the first node 1101 from being outputtedvia the second node 1102 when switch arm 1105 is in an OFF state (e.g.,when the one or more FETs is in an OFF state).

As illustrated in FIG. 9, the switch arm 1105 is coupled in parallelwith the distorter arm 1103 (e.g., a compensation circuit). Thedistorter arm 1103 includes a FET and is coupled to the switch arm 1105at an input side (e.g., a side coupled to the input node 1101) through aDC-blocking capacitor C1. The distorter arm 1103 is directly coupled tothe switch arm 1105 on an output side (e.g., a side coupled to theoutput node 1102). The switch circuit 1100 includes an inductor L1coupled to a reference potential node, the inductor L1 coupled at anode/junction between the output node 1102 and the output of both theswitch arm 1105 and the distorter arm 1103. The inductor L1 can beconfigured to direct DC signals to the reference potential node,providing an AC signal to the output node 1102 without or substantiallywithout a DC component. The distorter arm 1103 includes a DC source toprovide a bias voltage or current to the distorter FET in the distorterarm 1103. The switch arm 1105 and the distorter arm 1103 are separatefor DC signals due to the DC-blocking capacitor C1.

In some embodiments, the node 1101 may receive a signal (e.g., an RFsignal) having a power value and the node 1102 may output the signalwhen the switch arm 1105 is in an ON state. The number of FETs in theswitch arm 1105 may be selected to allow the switch circuit 1100 tohandle the power (e.g., power value) of the signal.

In some embodiments, the distorter arm 1103 may compensate for anon-linearity effect generated by the FETs of the switch arm 1105 whenit is in an ON state (e.g., when the FETs of the switch arm 1105 receivean RF signal from the node 1101 and provide the RF signal to the node1102). The distorter arm 1103 may compensate for the non-linearityeffect generated by the switch arm 1105 independent of (e.g., regardlessof) the frequency of the signal (e.g., RF signal) received by the switcharm 1105 (via node 1101) and provided to the node 1102.

The switch circuit 1100 can include a control module 1146 configured tocontrol operation of one or more of: the FET(s) of the switch arm 1105,the FET(s) of the distorter arm 1103, a bias supply of the switch arm1105, and the DC supply of the distorter arm 1103. For example, thecontrol module 1146 may place the FET(s) of the switch arm 1105 in theON state (e.g., may turn on the FET(s)). The control module 1146 mayalso place the distorter FET(s) of the distorter arm 1103 in the ONstate when the switch arm is in the ON state. The control module 1146may further control the DC supply to provide a targeted bias voltage orcurrent to the distorter FET(s). The control module 1146 may furthercontrol the bias supply to provide a targeted bias voltage or current tothe switch arm FET(s). In another example, the control module 1146 mayplace the switch arm 1105 in the OFF state (e.g., may turn off theFET(s)). The control module 1146 may also place the distorter FET(s) ofthe distorter arm 1103 in the OFF state when the switch arm 1105 is inthe OFF state. However, in various embodiments, the distorter FET(s) mayremain in the ON state when the switch arm 1105 is in the OFF state. Thecontrol module 1146 may be hardware (e.g., circuitry, dedicated logic,programmable logic, microcode, a processor, a field-programmable gatearray (FPGA), an application-specific integrated circuit (ASIC), etc.),software (e.g., instructions run on a processor), firmware, or acombination thereof. The control module 1146 may be part of the switchcircuit 1100 or may be separate from the switch circuit 1100 (e.g., thecontrol module 1146 may reside in another component/circuit/module).

In some embodiments, the switch circuit 1100 may also include one ormore bias/coupling circuits (as discussed in more detail in U.S. Pat.Pub. No. 2014/0009214). For example, a coupling circuit (discussed inmore detail in U.S. Pat. Pub. No. 2014/0009214) may be coupled to one ormore bodies of one or more of the FETs in the switch arm 1105 and/or thedistorter arm 1103.

The distorter arm 1103 an be configured to compensate for non-linearityin the switch arm 1105. For a FET in its ON state, the drain current,Id, increases almost linearly with the drain-source voltage, Vds, untilsaturation. FIG. 10 illustrates curves for the third derivative of thedrain current, gd3, as a function of drain-source voltage, Vds or Vd.The third derivative, gd3, is related to third order intermodulationdistortion, IMD3. As seen from the plot in FIG. 10, gd3 relates to aphysical size of the FET. The plot in FIG. 10 illustrates dependence ofgd3 on gate width size, ranging from 2 μm to 10 μm.

FIGS. 11A-11C illustrate plots showing compensation of gd3 of a switcharm having a stack of FETs by a distorter arm having one or more FETs.On the left of each of FIGS. 11A-11C, a plot is shown with the switcharm gd3 and the distorter arm gd3, as labeled in the plots. On the rightof each of FIGS. 11A-11C, a plot is shown with the fundamental signaloutput from the switch circuit (labeled “fund”) and the composite gd3signal as a function of Vd. FIG. 11A illustrates a circumstance wherethere is under-compensation of the switch gd3 by the distorter arm. FIG.11B illustrates a circumstance where the distorter arm gd3 compensatesfor the switch arm gd3 over a range of Vd values (e.g., between thepoints labeled m4 and m5). FIG. 11C illustrates a circumstance where thedistorter arm gd3 over-compensates for the switch arm gd3 so that thereare a couple of good compensation points (labeled m4 and m5) but betweenthese points there is not a good compensation. Thus, the distorter armcan be tuned to provide a window of compensation for non-linearityeffects in the switch arm. The FETs of the distorter arm can be tuned toprovide targeted compensation through selection of the size of theFET(s) used in the distorter arm as well as the bias voltage or currentprovided to the FET(s).

The plots in FIGS. 11A-11C were generated using simulations of FETs inthe switch arm and the distorter arm. For the switch arm, the simulationincluded 12 FETs connected in series, each FET having a gate width ofabout 3.5 mm. For the distorter arm, a single FET was used with a gatewidth of about 20 μm. In addition, the gd3 of the switch arm in theleft-hand plots of FIGS. 11A-11C are actually the inverse of the gd3 ofthe switch arm (e.g., −1 times the actual gd3 values) to better showwhere good gd3 compensation occurs (e.g., where the two lines in thegraph intersect or are near one another).

FIG. 12 illustrates results of a simulation of the switch circuit 1100described herein with reference to FIG. 11, operating to switch signalswith two fundamental frequencies represented by the two tallest linesjust below 2 GHz. In the top plot, signal power is illustrated as afunction of frequency for the switch circuit where the distorter arm isnot present. In the bottom plot, the signal power is illustrated as afunction of frequency for the switch circuit with a distorter arm. Inthe switch arm, Vd is equal to about 0 and in the distorter arm there isa small drain-source voltage, Vd #0. The simulation illustrates that thedistorter arm reduces third-order intermodulation distortion(represented by the change in power from the point m4 in the top plot tothe point m3 in the bottom plot). In certain embodiments, the switchcircuit 1100 increases harmonic distortion with the distortion armincluded (represented by the change in power from the point m5 in thetop plot to the point m1 in the bottom plot).

It may be beneficial to not increase or to reduce harmonic distortion inswitching circuits in addition to reducing IMD3 distortion. Accordingly,FIG. 13 illustrates an example switch circuit 1300 that includes dualparallel distorter arms 1303 a, 1303 b in parallel with a switch arm1305 that is configured to reduce or at least not significantly increaseharmonic distortion while decreasing IMD3 non-linearity in the switchcircuit 1300. The switch circuit 1300 includes input node 1301, outputnode 1302, and inductor L1 similar to the switch circuit 1100 describedherein with reference to FIG. 11. The switch arm 1305 is the same orsimilar to the switch arm 1105 described herein with reference to FIG.11, including one or more FETs to selectively pass signals from theinput node 1301 to the output node 1302. Each distorter arm 1303 a, 1303b is the same or similar to the distorter arm 1103 described herein withreference to FIG. 11 and are coupled to the switch arm 1305 throughrespective DC-blocking capacitors C1, C2. However, the distorter arms1303 a, 1303 b differ in that they are biased in opposite ways so thateven-order harmonics effectively or substantially cancel. For thedistorter arms 1303 a, 1303 b, the absolute value of the bias is thesame, but with opposite signs. This is shown in the switch circuit 1300by the power supplies in the respective distorter arms 1303 a, 1303 bbeing configured to provide opposite biasing to the respective FETs. Thecontrol module 1346 operates similarly to the control module 1146described herein with reference to FIG. 11, except that the controlmodule 1346 controls the dual distorter arms 1303 a, 1303 b rather thana single distorter arm. Due at least in part to the symmetry of thecircuit 1300, even-order harmonics can be canceled out. Furthermore,IMD3 of the circuit 1300 can be reduced due at least in part to thedistorter arms 1303 a, 1303 b providing compensating gd3 signals to becombined with the gd3 of the switch arm 1305.

FIG. 14 illustrates results of a simulation of the switch circuit 1300described herein with reference to FIG. 13, operating to switch signalswith two fundamental frequencies represented by the two tallest linesjust below 2 GHz. In the top plot, signal power is illustrated as afunction of frequency for the switch circuit where the dual distorterarms are not present. In the bottom plot, the signal power isillustrated as a function of frequency for the switch circuit with thedual distorter arms. In the switch arm, Vd is equal to about 0 and inthe distorter arms there are small drain-source voltage, Vd #0, withequal magnitude and opposite signs. The simulation illustrates that thedual distorter arms reduce third-order intermodulation distortion(represented by the change in power from the point m4 in the top plot tothe point m3 in the bottom plot) and does not significantly affectharmonic distortion (represented by the change in power from the pointm5 in the top plot to the point m2 in the bottom plot).

FIG. 15 illustrates an example switch circuit 1500 that includes dualparallel distorter arms 1503 a, 1503 b in parallel with a switch arm1505 that is configured to reduce or at least not significantly increaseharmonic distortion while decreasing IMD3 non-linearity in the switchcircuit 1500. The switch arm 1505 includes twelve 3.5 mm FETs and arebiased with switch voltage Vs. Each distorter arm 1503 a, 1503 bincludes a single 3.75 μm FET, meaning that the FET in each distorterarm is about 1000 times smaller than the FETs of the switch arm 1505.Accordingly, it is to be understood that the IMD3 non-linearities of theswitching circuits described herein can be reduced using FETs that areorders of magnitude smaller than the FETs being used to switch RFsignals in the switching circuit.

The switch circuit 1500 includes input node 1501 and output node 1502configured respectively to receive an input signal and to output anoutput signal. At the input node 1501, the switch circuit 1500 includesa DC-blocking capacitor C1 and a DC feed inductor L3. Similarly, theoutput node 1502 includes a DC-blocking capacitor C2 and a DC feedinductor L4. The DC-blocking capacitors C1, C2 and DC feed inductors L3,L4 operate to filter DC signals out so that the switch circuit 1500provides AC signals that are substantially free from DC offset voltagesto the switch arm 1505 and at the output node 1502.

Each distorter arm 1503 a, 1503 b receives a bias voltage from a voltagesource, Vdd. The voltage source, Vdd, provides current and voltage tothe distorter arms 1503 a, 1503 b with the same magnitude but oppositebias. Between the voltage source, Vdd, and each distorter arm 1503 a,1503 b there is an inductor L1, L2. Furthermore, there are DC-blockingcapacitors that couple the source terminals of the respective FETs ofthe distorter arms 1503 a, 1503 b to the switch arm 1505. The FETs ofthe distorter arms 1503 a, 1503 b receive gate bias voltages, Vgg, andbody bias voltages, Vbb, from one or more voltage supplies.

By way of example and not intended to limit the scope of the disclosure,example values of the components of the switch circuit 1500 areprovided. The capacitors C3, C4 can each have a value of about 100 pF.The inductors L1, L2 can each have a value of about 100 nH. Theinductors L3, L4 can each have a value of about 20 nH. In someembodiments, increasing the capacitance of capacitors C3, C4 improvesthe cancellation of IMD3 non-linearity effects of the switch circuit1500. For example, where the capacitors have a value of about 100 nH,IP3 of the circuit 1500 is about −85 dBm, where the capacitors have avalue of about 250 nH, IP3 of the circuit 1500 is about −90 dBm, andwhere the capacitors have a value of about 500 nH, IP3 of the circuit1500 is about −95 dBm.

FIG. 16 illustrates results of a simulation of the switch circuit 1500described herein with reference to FIG. 15, operating to switch signalswith two fundamental frequencies represented by the two tallest linesjust below 2 GHz (e.g., 1.85 GHz at point m9). The plot representsperformance of the switch with the dual distorter arms 1503 a, 1503 band can be compared to the top plots in FIGS. 12 and 14 which representperformance of the switch circuit without any distorter arm. In theplot, signal power is illustrated as a function of frequency for theswitch circuit with the dual distorter arms. In the switch arm, Vd isequal to about 0 and in the distorter arms there are small drain-sourcevoltage, Vd #0, with equal magnitude and opposite signs. The simulationillustrates that the dual distorter arms reduce third-orderintermodulation distortion (represented by the change in power from thepoint m4 in the plots in FIGS. 12 and 14 to the point m8 in the plot ora change from −73.492 dBm to −99.552 dBm) and slightly increasesharmonic distortion (represented by the change in power from the pointm5 in the plots in FIGS. 12 and 14 to the point m10 in the plot or achange from −94.460 dBm to −91.291).

In some embodiments, putting the switch in an OFF state from an ON statecan induce a large voltage drop across the FETs in the distorter arms.If that voltage drop is sufficiently high, the FETs in the distorterarms may break down. By increasing the number of FETs in each distorterarm, the effective break-down voltage of the distorter arm may beincreased. Accordingly, FIG. 17 illustrates a portion of a switchcircuit 1700 having a switch arm 1705 and a distorter arm 1703 betweenan input node 1701 and an output node 1702. The switch arm 1705 includestwelve 3.5 mm FETs and the distorter arm 1703 includes four smaller(e.g., 3.75 μm) FETs. It is to be understood that the number of FETs inthe distorter arm 1703 can be different from four, being less than fouror greater than four. It should also be understood that the switchcircuit 1700 can include dual distorter arms 1703 although a singledistorter arm is illustrated in FIG. 17. By increasing the number ofFETs in the distorter arm 1703, the switch circuit 1700 can be morerobust when switching from an ON state to an OFF state. In the switchcircuit, Vds for the switch arm 1705 can be 0 (e.g., Vds=0) and Vds forthe distorter arm 1703 can be different from 0 (e.g., Vds≠0).

Table 1 provides simulated results for varying parameters of thedistorter arm 1703 in the switch circuit 1700. By increasing the numberof FETs in the distorter arm, resistance to voltage break down can beincreased. Increasing the number of FETs may also increase the powerrequirements of the switch circuit.

TABLE 1 Stack Height 1 2 3 Wtot (μm) 3.75 16 92 Vds (V) 0.45 0.6 1.1 Ids(mA) 1.5 7.0 37 DC Power (mW) 1.4 8.4 81.4

It may be advantageous to reduce the power requirements of a switchcircuit while maintaining the ability to have a robust distorter armwhen switching from an ON state to an OFF state. Accordingly, FIG. 18illustrates an example switch circuit 1800 with a switch arm 1805,distorter arm 1803, and a voltage buffer 1804 in series with thedistorter arm 1803. The switch circuit 1800 includes input node 1801 andoutput node 1802 to respectively receive an input signal and to outputan output signal. The switch arm 1805 includes twelve 3.5 mm FETs andthe distorter arm 1803 includes a single smaller FET (e.g., 6.2 μm). Thevoltage buffer 1804 includes a stack of twelve FETs, individual FETs inthe stack being bigger than the distorter FET and smaller than a switcharm FET. In some embodiments, the FETs in the voltage buffer 1804 caneach have a gate width of about 200 μm.

In the OFF state, the voltage buffer 1804 absorbs the majority of thevoltage drop, thereby protecting the distorter FET in the distorter arm1803. Table 2 provides bias configurations of the switch arm 1805,distorter arm 1803, and voltage buffer 1804 in an ON state and OFF stateof the switch circuit 1800.

TABLE 2 Switch Buffer Distorter ON state ON ON ON, Vds ≠ 0 OFF state OFFOFF ON, Vds = 0

As can be seen in Table 2, the distorter arm 1803 can remain in an ONstate even when the switch circuit switches to an OFF state. Because thevoltage buffer 1804 is in series with the distorter arm 1803 andincludes a plurality of larger FETs, the majority of the voltage dropoccurs across the voltage buffer 1804, protecting the distorter FET inthe distorter arm 1803 from breaking down due to a large voltage swingin the transition from the ON state to the OFF state. In the switchcircuit, the FETs in the voltage buffer 1804 have Vds equal to 0, likethe FETs of the switch arm 1805. The FET of the distorter arm 1803always remains in the ON state, but the voltage Vds changes from 0 inthe OFF state to non-zero in the ON state. In the ON state, the majorityof the voltage drop across the arm parallel to the switch arm 1805 is onthe distorter arm 1803 rather than the voltage buffer 1804. Because themajority of the voltage drop occurs on the distorter arm 1803 ratherthan the voltage buffer 1804, the input power is used to generatesignals that reduce or cancel IMD3 non-linearities in the switch circuit1800. In the OFF state, the majority of the voltage drop is on thevoltage buffer 1804 due at least in part to maintaining the distorterFET in an ON state. Accordingly, the distorter FET in the distorter arm1803 is protected and the IMD generated by the distorter arm 1803 isnegligible in the switch circuit 1800 OFF state.

FIG. 19 illustrates a plot of the DC power consumption as a function ofgate width of the voltage buffer. As the gate width increases, the powerconsumption decreases. This is due at least in part to increasing thefraction of voltage drop across the distorter FET in the distorter arm1803 in the ON state relative to the voltage buffer 1804. In someembodiments, the power consumption per DPDT can be reduced to be lessthan or equal to about 3 mW.

Table 3 summarizes the results of simulating the performance of a switchcircuit having a switch arm, distorter arm and a voltage bufferconfigured in a manner similar to the switch circuit 1800 describedherein in FIG. 18, with the switch circuit operated as a dual pole, dualthrow (DPDT) switch. The inclusion of a distorter arm with voltagebuffer decreases IMD3 of the DPDT switch by more than 20 dB.

TABLE 3 On Arm Off Arm DPDT No Distorter  −75 dB −99 dB −75 dB Distorter−121 dB −99 dB −99 dB

FIG. 20 illustrates various plots of performance of the switch circuitconfigured as a DPDT switch. In each plot, comparisons are made betweena DPDT switch with and without a distorter, as described herein. Itshould be noted that the simulated DPDT switch with distorter wastailored to provide enhanced performance characteristics at about 25 dBmpower, 50Ω load resistance, and 1.8 GHz frequency. These operatingpoints can be changed to provide enhanced performance characteristics atdifferent powers, load resistances, and/or frequencies. In the plot ofIMD3 as a function of Vds, it is shown that there is a range of Vdsvalues that provide beneficial or targeted IMD3 cancellation (e.g.,between about 0.4 V and 0.5 V). These plots illustrate that thedistorter arms disclosed herein can improve the operation of switchingcircuits over a wide range of input power, carrier frequency, signalbandwidth, operating temperature, mismatch, Vds, and the like.

FIG. 21 illustrates another example switch circuit 2100 configuredsimilarly to the switch circuit 1800 but having a non-linear resistor inthe distorter arm 2103 rather than a FET. As described herein withreference to FIG. 18, the distorter arm 1803 with distorter FET put thedistorter FET in the ON state regardless of whether the switch circuitoperated in the ON state or OFF state. Accordingly, the FET can bereplaced with a non-linear resistor, as illustrated in the switchcircuit 2100 of FIG. 21.

FIG. 22 illustrates an example biasing circuit 2200 for a switchcircuit, as described herein. The biasing circuit 2200 is configured tobias the distorter arms 2203 and the voltage buffers 2204 and not aswitch arm. This is because, in some embodiments, it is undesirable tobias the switch arm. The biasing circuit 2200 includes distorters 2203a, 2203 b having source, drain, gate and body terminals. Similarly, thebiasing circuit 2200 includes buffers 2204 a, 2204 b having source,gate, and drain terminals. For reference, input node 2201 and outputnode 2202 are shown. Voltage Vbb is provided to the body terminals ofthe distorter arms 2203 a, 2203 b. A power supply provides a DC voltageto the gate terminals of the distorter arms 2203 a, 2203 b. Similarly,power supplies provide voltages to the gate terminals of the voltagebuffers 2204 a, 2204 b. The biasing circuit includes DC-blockingcapacitors C1, C2 at the input node 2201 and output node 2202,respectively.

The biasing circuit 2200 includes current sources to drive currents tothe distorters 2203 a, 2203 b, as shown. The current sources cangenerate a current loop in the biasing circuit 2200, where the currentloop is formed with the two distorters 2203 a, 2203 b and the twocurrent sources. Due at least in part to the high impedance of thecurrent sources, the RF choke between the DC bias source and thedistorters 2203 a, 2203 b can be reduced or eliminated.

In some embodiments, the switch circuits described herein may alsoinclude one or more bias/coupling circuits (as discussed in more detailin U.S. Pat. Pub. No. 2014/0009214). For example, a coupling circuit(discussed in more detail in U.S. Pat. Pub. No. 2014/0009214) may becoupled to one or more bodies of one or more of the FETs in the switcharms, distorter arms, and/or voltage buffers. One having ordinary skillin the art understands that the various values for the capacitancesand/or resistances may be used in the distorter arms disclosed herein.

In some implementations, the foregoing example configurations describedin reference to FIGS. 9, 13, 15, 17, 18 and 21 (and generally describedherein) may allow significant or substantially complete cancelation ofnon-linearity effects associated with one or more SOI FET based RFswitches.

Examples of Implementations in Products

Various examples of FET-based switch circuits and bias/couplingconfigurations described herein can be implemented in a number ofdifferent ways and at different product levels. Some of such productimplementations are described by way of examples.

Semiconductor Die Implementation

FIGS. 23A-23D schematically show non-limiting examples of suchimplementations on one or more semiconductor die. FIG. 23A shows that insome embodiments, a switch circuit 120 and a bias/coupling circuit 150having one or more features as described herein can be implemented on adie 800. In addition, a distortion arm and/or voltage buffer (e.g.,distortion arm 903 illustrated in FIG. 9, distortion arms 1303 a, 1303 billustrated in FIG. 13, distortion arms 1503 a, 1503 b illustrated inFIG. 15, distortion arm 1703 illustrated in FIG. 17, distortion arm 1803and voltage buffer 1804 illustrated in FIG. 18, distortion arm 2103 andvoltage buffer 2104 illustrated in FIG. 18, and biasing circuit 2200illustrated in FIG. 22) may also be implemented on the die 800. FIG. 23Bshows that in some embodiments, at least some of the bias/couplingcircuit 150 can be implemented outside of the die 800 of FIG. 23A. Inaddition, at least some or part of a distortion arm and/or voltagebuffer (e.g., distortion arm 903 illustrated in FIG. 9, distortion arms1303 a, 1303 b illustrated in FIG. 13, distortion arms 1503 a, 1503 billustrated in FIG. 15, distortion arm 1703 illustrated in FIG. 17,distortion arm 1803 and voltage buffer 1804 illustrated in FIG. 18,distortion arm 2103 and voltage buffer 2104 illustrated in FIG. 18, andbiasing circuit 2200 illustrated in FIG. 22) may also be implementedoutside of the die 800.

FIG. 23C shows that in some embodiments, a switch circuit 120 having oneor more features as described herein can be implemented on a second die800 b, and a bias/coupling circuit 150 having one or more features asdescribed herein can be implemented on a first die 800 a. In addition, adistortion arm and/or voltage buffer (e.g., distortion arm 903illustrated in FIG. 9, distortion arms 1303 a, 1303 b illustrated inFIG. 13, distortion arms 1503 a, 1503 b illustrated in FIG. 15,distortion arm 1703 illustrated in FIG. 17, distortion arm 1803 andvoltage buffer 1804 illustrated in FIG. 18, distortion arm 2103 andvoltage buffer 2104 illustrated in FIG. 18, and biasing circuit 2200illustrated in FIG. 22) may also be implemented on the first die 800 a.FIG. 23D shows that in some embodiments, at least some of thebias/coupling circuit 150 can be implemented outside of the first die800 a of FIG. 23C. In addition, at least some or part of a distortionarm and/or voltage buffer (e.g., distortion arm 903 illustrated in FIG.9, distortion arms 1303 a, 1303 b illustrated in FIG. 13, distortionarms 1503 a, 1503 b illustrated in FIG. 15, distortion arm 1703illustrated in FIG. 17, distortion arm 1803 and voltage buffer 1804illustrated in FIG. 18, distortion arm 2103 and voltage buffer 2104illustrated in FIG. 18, and biasing circuit 2200 illustrated in FIG. 22)may also be implemented outside of the first die 800 a.

Packaged Module Implementation

In some embodiments, one or more die having one or more featuresdescribed herein can be implemented in a packaged module. An example ofsuch a module is shown in FIGS. 24A (plan view) and 24B (side view).Although described in the context of both of the switch circuit and thebias/coupling circuit being on the same die (e.g., example configurationof FIG. 23A), it will be understood that packaged modules can be basedon other configurations.

A module 810 is shown to include a packaging substrate 812. Such apackaging substrate can be configured to receive a plurality ofcomponents, and can include, for example, a laminate substrate. Thecomponents mounted on the packaging substrate 812 can include one ormore dies. In the example shown, a die 800 having a switching circuit120 and a bias/coupling circuit 150 is shown to be mounted on thepackaging substrate 812. The die 800 can be electrically connected toother parts of the module (and with each other where more than one dieis utilized) through connections such as connection-wirebonds 816. Suchconnection-wirebonds can be formed between contact pads 818 formed onthe die 800 and contact pads 814 formed on the packaging substrate 812.In some embodiments, one or more surface mounted devices (SMDs) 822 canbe mounted on the packaging substrate 812 to facilitate variousfunctionalities of the module 810.

In some embodiments, the packaging substrate 812 can include electricalconnection paths for interconnecting the various components with eachother and/or with contact pads for external connections. For example, aconnection path 832 is depicted as interconnecting the example SMD 822and the die 800. In another example, a connection path 832 is depictedas interconnecting the SMD 822 with an external-connection contact pad834. In yet another example a connection path 832 is depicted asinterconnecting the die 800 with ground-connection contact pads 836.

In some embodiments, a space above the packaging substrate 812 and thevarious components mounted thereon can be filled with an overmoldstructure 830. Such an overmold structure can provide a number ofdesirable functionalities, including protection for the components andwirebonds from external elements, and easier handling of the packagedmodule 810.

FIG. 25 shows a schematic diagram of an example switching configurationthat can be implemented in the module 810 described in reference toFIGS. 24A and 24B. In the example, the switch circuit 120 is depicted asbeing an SP9T switch, with the pole being connectable to an antenna andthe throws being connectable to various Rx and Tx paths. Such aconfiguration can facilitate, for example, multi-mode multi-bandoperations in wireless devices.

The module 810 can further include an interface for receiving power(e.g., supply voltage VDD) and control signals to facilitate operationof the switch circuit 120 and/or the bias/coupling circuit 150. In someimplementations, supply voltage and control signals can be applied tothe switch circuit 120 via the bias/coupling circuit 150.

FIG. 26 shows that in some embodiments, some or all of the deviceshaving one or more features as described herein may be implemented in amodule. Such a module may be, for example, a front-end module (FEM). Inthe example of FIG. 26, a radio frequency (RF) module 300 can include apackaging substrate 302, and a number of components may be mounted onsuch a packaging substrate. For example, a front-end power managementintegrated circuit (FE-PMIC) component 304, a power amplifier assembly306, a match component 308, and a duplexer assembly 310 may be mountedand/or implemented on and/or within the packaging substrate 302. TheFE-PMIC component 304 includes a supply 100 which may be a power supply(e.g., a battery, a voltage/power source) and/or may be coupled to apower supply. Other components such as a number of surface mounttechnology (SMT) devices 314 and an antenna switch module (ASM) 312 canalso be mounted on the packaging substrate 302. Although all of thevarious components are depicted as being laid out on the packagingsubstrate 302, it will be understood that some component(s) may beimplemented over other component(s). In some embodiments, the componentsof the RF module 300 and one or more serial buses/interfaces (e.g., aRFFE bus/interface) used by the components of the RF module 300 mayimplement and/or perform one or more features as described herein.

Wireless Device Implementation

In some implementations, a device and/or a circuit having one or morefeatures described herein can be included in an RF device such as awireless device. Such a device and/or a circuit can be implementeddirectly in the wireless device, in a modular form as described herein,or in some combination thereof. In some embodiments, such a wirelessdevice can include, for example, a cellular phone, a smart-phone, ahand-held wireless device with or without phone functionality, awireless tablet, etc.

FIG. 27 schematically depicts an example wireless device 900 having oneor more advantageous features described herein. In the context ofvarious switches and various biasing/coupling configurations asdescribed herein, a switch 120 and a bias/coupling circuit 150 can bepart of a module 810. In some embodiments, such a switch module canfacilitate, for example, multi-band multi-mode operation of the wirelessdevice 900.

In the example wireless device 900, a power amplifier (PA) module 916having a plurality of PAs can provide an amplified RF signal to theswitch 120 (via a duplexer 920), and the switch 120 can route theamplified RF signal to an antenna. The PA module 916 can receive anunamplified RF signal from a transceiver 914 that can be configured andoperated in known manners. The transceiver can also be configured toprocess received signals. The transceiver 914 is shown to interact witha baseband sub-system 910 that is configured to provide conversionbetween data and/or voice signals suitable for a user and RF signalssuitable for the transceiver 914. The transceiver 914 is also shown tobe connected to a power management component 906 that is configured tomanage power for the operation of the wireless device 900. Such a powermanagement component can also control operations of the basebandsub-system 910 and the module 810.

The baseband sub-system 910 is shown to be connected to a user interface902 to facilitate various input and output of voice and/or data providedto and received from the user. The baseband sub-system 910 can also beconnected to a memory 904 that is configured to store data and/orinstructions to facilitate the operation of the wireless device, and/orto provide storage of information for the user.

In some embodiments, the duplexer 920 can allow transmit and receiveoperations to be performed simultaneously using a common antenna (e.g.,924). In FIG. 27, received signals are shown to be routed to “Rx” paths(not shown) that can include, for example, a low-noise amplifier (LNA).

A number of other wireless device configurations can utilize one or morefeatures described herein. For example, a wireless device does not needto be a multi-band device. In another example, a wireless device caninclude additional antennas such as diversity antenna, and additionalconnectivity features such as Wi-Fi, Bluetooth, and GPS.

General Comments

Unless the context clearly requires otherwise, throughout thedescription and the claims, the words “comprise,” “comprising,” and thelike are to be construed in an inclusive sense, as opposed to anexclusive or exhaustive sense; that is to say, in the sense of“including, but not limited to.” The word “coupled”, as generally usedherein, refers to two or more elements that may be either directlyconnected, or connected by way of one or more intermediate elements.Additionally, the words “herein,” “above,” “below,” and words of similarimport, when used in this application, shall refer to this applicationas a whole and not to any particular portions of this application. Wherethe context permits, words in the above Detailed Description using thesingular or plural number may also include the plural or singular numberrespectively. The word “or” in reference to a list of two or more items,that word covers all of the following interpretations of the word: anyof the items in the list, all of the items in the list, and anycombination of the items in the list.

The above detailed description of embodiments of the disclosure is notintended to be exhaustive or to limit the disclosure to the precise formdisclosed above. While specific embodiments of, and examples for, thedisclosure are described above for illustrative purposes, variousequivalent modifications are possible within the scope of the invention,as those skilled in the relevant art will recognize. For example, whileprocesses or blocks are presented in a given order, alternativeembodiments may perform routines having steps, or employ systems havingblocks, in a different order, and some processes or blocks may bedeleted, moved, added, subdivided, combined, and/or modified. Each ofthese processes or blocks may be implemented in a variety of differentways. Also, while processes or blocks are at times shown as beingperformed in series, these processes or blocks may instead be performedin parallel, or may be performed at different times.

The teachings of the disclosure provided herein can be applied to othersystems, not necessarily the system described above. The elements andacts of the various embodiments described above can be combined toprovide further embodiments.

While certain embodiments of the disclosure have been described, theseembodiments have been presented by way of example only, and are notintended to limit the scope of the disclosure. Indeed, the novel methodsand systems described herein may be embodied in a variety of otherforms; furthermore, various omissions, substitutions and changes in theform of the methods and systems described herein may be made withoutdeparting from the spirit of the disclosure. The accompanying claims andtheir equivalents are intended to cover such forms or modifications aswould fall within the scope and spirit of the disclosure.

What is claimed is:
 1. A radio-frequency (RF) switch comprising: aswitch arm having a set of switch field-effect transistors (FETs)coupled in series and disposed between a first node and a second node,individual switch FETs of the set of switch FETs having a switch FETgate width; a distorter arm coupled in parallel to the switch arm, thedistorter arm having a distorter FET with a distorter FET gate width,the distorter arm configured to compensate a non-linearity effectgenerated by the set of switch FETs; and a voltage buffer coupled inseries with the distorter arm and in parallel with the switch arm, thevoltage buffer having a set of buffer FETs coupled in series, individualbuffer FETs of the set of buffer FETs having a buffer FET gate widththat is larger than the distorter FET gate width and smaller than theswitch FET gate width, the voltage buffer configured to protect thedistorter arm from large voltage swings as the RF switch transitionsbetween ON and OFF states.
 2. The RF switch of claim 1 wherein thedistorter FET gate width is smaller than about 10 μm and the switch FETgate width is larger than about 1 mm.
 3. The RF switch of claim 2wherein the buffer FET gate width is about 200 mm.
 4. The RF switch ofclaim 1 wherein the distorter FET gate width is about 500 times smallerthan the switch FET gate width.
 5. The RF switch of claim 1 wherein theset of switch FETs includes at least 12 FETs.
 6. The RF switch of claim5 wherein the set of buffer FETs includes at least 12 FETs.
 7. The RFswitch of claim 6 wherein the distorter arm includes a single distorterFET.
 8. The RF switch of claim 1 wherein, in an ON state, the voltagebuffer, the switch arm, and the distorter arm are configured to be in anON state.
 9. The RF switch of claim 8 wherein, in an OFF state, thevoltage buffer and the switch arm are configured to be in an OFF stateand the distorter arm is configured to be in an ON state.
 10. The RFswitch of claim 1 wherein the distorter arm is configured to generatethird-order intermodulation distortion to reduce a non-linearity effectgenerated by the set of switch FETs.
 11. The RF switch of claim 1further comprising a control module configured to control operation ofthe switch arm, the distorter arm, and the voltage buffer.
 12. The RFswitch of claim 1 further comprising a biasing circuit configured tobias the distorter arm and the voltage buffer.
 13. The RF switch ofclaim 12 wherein the biasing circuit is not configured to bias theswitch arm.
 14. The RF switch of claim 12 wherein the biasing circuit isconfigured to provide a buffer gate voltage to gate terminals of the setof buffer FETs.
 15. The RF switch of claim 12 wherein the biasingcircuit is configured to provide a distorter gate voltage to a gateterminal of the distorter FET.
 16. The RF switch of claim 12 wherein thebiasing circuit includes a current source to drive current to thedistorter arm.
 17. The RF switch of claim 1 wherein the set of switchFETs comprise silicon-on-insulator (SOI) FETs.
 18. A radio-frequency(RF) switch module comprising: a packaging substrate configured toreceive a plurality of components; a semiconductor die mounted on thepackaging substrate, the semiconductor die including a set of switchfield-effect transistors (FETs) in a switch arm, the set of switch FETseach having a switch FET gate width; a distorter arm mounted on thepackaging substrate coupled in parallel with the switch arm, thedistorter arm having a distorter FET with a distorter FET gate width,the distorter arm configured to compensate a non-linearity effectgenerated by the switch arm; and a voltage buffer mounted on thepackaging substrate coupled in parallel with the switch arm and inseries with the distorter arm, the voltage buffer including a set ofbuffer FETs each having a buffer FET gate width such that the buffer FETgate width is greater than the distorter FET gate width and less thanthe switch FET gate width.
 19. The RF switch module of claim 18 whereinthe distorter arm and the voltage buffer are implemented on thesemiconductor die.
 20. A wireless device comprising: a transceiverconfigured to process radio-frequency (RF) signals; an antenna incommunication with the transceiver configured to facilitate transmissionof an amplified RF signal; a power amplifier connected to thetransceiver and configured to generate the amplified RF signal; and aswitch connected to the antenna and the power amplifier and configuredto selectively route the amplified RF signal to the antenna, the switchincluding a set of switch field-effect transistors (FETs) in a switcharm, the set of switch FETs each having a switch FET gate width; theswitch further including a distorter arm mounted on the packagingsubstrate coupled in parallel with the switch arm, the distorter armhaving a distorter FET with a distorter FET gate width, the distorterarm configured to compensate a non-linearity effect generated by theswitch arm; and the switch further including a voltage buffer mounted onthe packaging substrate coupled in parallel with the switch arm and inseries with the distorter arm, the voltage buffer including a set ofbuffer FETs each having a buffer FET gate width such that the buffer FETgate width is greater than the distorter FET gate width and less thanthe switch FET gate width.